The following calculation sheet is mostly useful for classic CAN as defined in ISO-11898 before 2015. For the new CAN FD as defined in ISO-11898:2015 work is in Progress. CiA provides the document CiA 601-3 CAN FD bit-timing recommendations.

By providing the input clock frequency feed into the CAN clock Pre-scaler, the desired Sample Point location and selecting the CAN family, this page calculates possible register values to program CAN controllers for typical bit rates.

You can use the table in NXP SJA1000 mode (Like Philips or Intel) for controllers like:

or select other CAN family types. The BOSCH C_CAN or D_CAN are often used in more modern implementations of different manufacturers( ST SPEAr, TI Sitara, ...) An explanation is given after the table (if calculation was called).

The table results in generic colums listing the values for number of tq, tseg1, tsegs, prescaler etc. and some hardware specifc register which can used to directly program the controller.

Clock Rate in MHz, from 1 to 300. Use the value of the clock rate at the first stage of the BaudRatePrescaler BTR, not the clock of the controller or crystal (typically for a 16 MHz clocked NXP SJA1000 use '8').
Sample-Point at: in %, from 50 to 90 (87.5 % is the preferred value used by CANopen and DeviceNet, 75% is the default value for ARINC 825).
SJW: numerical value from 1 to .. (1 is the preferred value used by CANopen and DeviceNet. The value is currently not used in all calculations, please look at the values used below the bit timing table.

The table will be calculated for all CANopen defined bit rates. If you like to have the calculation for one special arbitrary bit rate, enter the the value here in kbit/s

Debug: generates debugging information to the calculation after the table.

A table can be requested by passing parameters on the http request line like
http://www.bittiming.can-wiki.info/?CLK=8&ctype=Philips&calc=1 With possible parameters: CLK=, SJW=, SamplePoint=, ctype=, calc=. Where ctype is the controller type. If calc=1, calc is true, the table is immediately calculated and displayed.

Yellow background rows are settings with recommended values, with an bittime consisting of 16 time quanta tq (Number of time quanta). At the time this tool was first developed, this seems to be the best value. in these days where we talk about CAN FD, as much as possible time quanta should be used to construct an bit time.

Selected:

This table was generated using JavaScript and jQuery. (An older version written in Tcl was first published in 1998).

Copyright © 2013-2021 Heinz-Jürgen Oertel

All rights reserved.
If you find bugs in this service, please inform Me

The question arises: what exactly is the sample point? The picture shows you the time segments of a CAN-Bit as defined by ISO-11898.

sampling point
Sync_Seg:1 tq
Prop_Seg + Phase_Seg1:1 .. 16 tq
Phase_Seg2:1 .. 8 tq
(Table calculation uses Prop_Seg = 0)


A detailed description about setting the correct CAN bit timing is given in a paper by Florian Hartwich and Armin Bassemir by Robert Bosch: The Configuration of the CAN Bit Timing. And for CAN FD: Bit Time Requirements for CAN FD Florian Hartwich, Robert Bosch GmbH


Basically the CAN bit period can be subdivided into four time segments. Each time segment consists of a number of Time Quanta (tq). The Time Quanta is the smallest time unit for all configuration values.
  • SYNC_SEG is 1 Time Quantum long. It is used to synchronize the various bus nodes.
  • PROP_SEG is programmable to be 1, 2,... 8 Time Quanta long. It is used to compensate for signal delays across the network.
  • PHASE_SEG1 is programmable to be 1,2, ... 8 Time Quanta long. It is used to compensate for edge phase errors and may be lengthened during resynchronization.
  • PHASE_SEG2 (Seg 2) is the maximum of PHASE_SEG1 and the Information Processing Time long. It is also used to compensate edge phase errors and may be shortened during resynchronization. For this the minimum value of PHASE_SEG2 is the value of SJW.
  • Information Processing Time is less than or equal to 2 Time Quanta long.
  • The total number of Time Quanta has to be from 8 to 25. (Newer CAN controllers might allow other ranges. Check e.g. the BOSCH M_CAN.
  • The SJW ist not (yet) considered by the tool. Values are always zero, which means the Synchronization Jump Width is 1 tq. If a value is entered, it is only copied to the appropriate register.
  • SAM or (SAMP) determines the number of CAN bus samples taken per bit time. and sometimes offered to be configured

The calculated table shows (PROP_SEG + PHASE_SEG1) as Seg 1.
accuracy is the deviation, from the desired bit rate.

Programming of the Sample Point allows optimizing the Bit Timing: A late sampling for example allows a maximum bus length: an early sampling allows slower rising and falling edges.
The more difficult settings of bit timings and Sample Point are explained in The physical layer in the CAN FD world.

Allwinner Technology

Allwinner A20

Currently it is difficult to get a good documentation on the Allwinner A20 CAN module. Two different sources show two different results. The A20 manual Revision 1.0 (Feb 2013) chapter 6.16.3 shows a 16 bit Bit Timing Register.

The document "CAN Bus1.pdf" shows the same register picture while in section 1.5.6 the "CAN Bus Timing Register" description shows a 32 bit register which looks like:

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN_BUS_TIME - SAM PHSEG2 PHSEG1 SJW - BRP

This register layout was proved by an implementation of the can4linux device driver.

Analog Devices

BlackFin BF50x/BF60x

16 bit Bit CAN_CLK register setting BTR

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN_CLK     reserved BRP

16 bit Bit CAN_TIMING register setting SJW, SAM, TSEG2 and TSEG1

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN_TIMING reserved SJW SAM TSEG2 TSEG1

BlackFin BF70x

Analog Devices implemented the same CAN module as in the BlackFin BF50x series. Therefore the same bit timing register calculation can be used. But all registers are 32bit, with the highest 16 bits unused.

ADSP-CM40x

The ADSP-CM40x is a Mixed-Signal Control Processor with ARM Cortex-M4 core. Analog Devices implemented the same CAN module as in the BlackFin. Therefore the same bit timing register calculation can be used.

ATMEL

ATMEL AT91SAM9263

Only one 32 bit register is used. Because of the minimum information processing time of 2tq (IPT=2tq) phase2 must be at least 2 tq.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTP reserved SMP - BRP reserved SJW - PROPAG - PHASE1 - PHASE2

This register layout is the same for the
  • AT91SAM7A3
  • the AT91SAM7X (SAM7X512/256/128)
  • the SAMA5D3 Cortex®-A5 processor series
  • the SAM3X, SAM3A, ARM® Cortex®-M3 based
family.

ATMEL STR750

STR750 ARM7TDMI-based microcontroller family implements Bosch C-CAN Select BOSCH C_CAN to generate the bit timing values.

ATMEL CANary

FCAN is the input frequency used as table input.
The CANary module used by ATMEL for the T89C51(AT89C51CC02) and CAN-AVR family, uses three 8-bit registers to set-up the bit timing parameters required by the CAN protocol - CANBT1, CANBT2 und CANBT3. CANBT1 contains BRP, the bit timing prescaler at bits 1-6, value range 0-63. CANBT2 contains the programming time segment PRS = PROP_SEG (Bit 1-3) and CANBT3 contains the values for PHS1 = PHASE_SEG1 (Bit 1-3) and PHS2 = PHASE_SEG2 (Bit 4-6 in CANBT3).

  7 6 5 4 3 2 1 0
CANBT1 - BRP -
CANBT2 - SJW - PRS -
CANBT3 - PHS2 PHS1 SMP

For 125 kbit/s and 16 tq at 16 (8)Mhz
BRP = 3, PRS = 4, PHS1 = 7, PHS2 = 1

BOSCH

Bosch C_CAN

The C_CAN CAN Controller from Bosch was implemented in different CPUs. Therefor our table show the 8 bit values BTR0 und BTR1. But often the 16bit value is used:
Bittiming Register BTR = (BTR1 << 8) | BTR0

8 bit Bit Timing Register BTR1 and BTR0

  15 14 13 12 11 10 9 8
BTR1 - TSeg2 TSeg1
  7 6 5 4 3 2 1 0
BTR0 SJW=0 BRP

16 bit Bit Timing Register BTR

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTR - TSeg2 TSeg1 SJW BRP

Besides the standard Bit Rate Prescaler BRP, the C_CAN module has the BRP Extension Register BRPE. By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BRP (LSBs) is used.

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRPE reserved BRPE

Bosch D_CAN

The D_CAN CAN Controller from Bosch uses the same bit timing register model as the C_CAN module. The Texas Instruments Sitara AM335x combines it in one 32 bit register DCANBTR.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCANBTR reserved BRPE - TSeg2 TSeg1 SJW BRP
Combine the values as DCANBTR = (BRPE << 16) + BTR

Bosch M_CAN

The Bosch M_CAN CAN controller module ist the first one available supporting CAN FD and therefore needs a second bit rate specified for the fast part of the CAN data frame. Bit Timing is programmed via the Bit Timing & Prescaler Register (BTP). The CAN bit time may be programed in the range of 4 to 81 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 m_can_cclk periods. TSEG1 is the sum of Prop_Seg and Phase_Seg1. TSEG2 is Phase_Seg2.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTP reserved BRP reserved TSEG1 TSEG2 SJW

For the faster bit time in CAN FD mode, M_CAN maintains the aditional Fast Bit Timing & Prescaler Register (FBTP).

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBTP res TDCO TDC res FBPR res FTSEG1 res FTSEG2 res FSJW

Besides the typical values, prefixed with 'F' for 'fast', like FBRP, FTSEG1, FTSEG2 and FSJW, it has values for the Transceiver Delay Compensation Offset TDCO and a disable/enable bit for Transceiver Delay Compensation TDC.
The Fast Baud Rate Prescaler has valid values from 0 to 31. FTSEG1 from 1 to 15, and FTSEG2 from 0 to 7. For all of them the actual interpretation by the hardware of this values is such that one more than the value programmed here is used. Note: The bit rate configured for the CAN FD data phase via FBTP must be higher or equal to the bit rate configured for the arbitration phase via BTP.

To simplify programming the fast bit rate, the programm allows only the fast bit rate to be multiple of the arbitration bit rate.

Freescale is now (since 2015) NXP

The CAN protocol as such and the Freescale CAN implementations MCAN, TOUCAN, MSCAN08 and MSCAN12 are described in this paper. The Freescale application note discusses the CAN Bit Timing Requirements.

Freescale TouCAN/FlexCAN

The TouCAN module uses three 8-bit registers to set-up the bit timing parameters required by the CAN protocol. Control registers 1 and 2 (CANCTRL1, CANCTRL2) contain the PROPSEG = PROP_SEG( Bit 0-3 in CANCTRL1), PSEG1 = PHASE_SEG1 (Bit 3-5), PSEG2 = PHASE_SEG2 (Bit 0-2), und the RJW (Bit 6-7 in CANCTRL2) fields which allow the user to configure the bit timing parameters. The prescaler divide register (PRESDIV) allows the user to select the ratio used to derive the clock from the system clock. According to AN1776 the TouCAN module needs at least 9 time quante per bit.
The more modern FlexCAN implementations are using the 32 bit Control Register (CTRL) to program bit timing, but much more. CTRL contains as well the bit fields PRESDIV (8 bit pre-scaler), PROPSEG ( 3 bit), PSEG1 ( 3 bit) and PSEG2 (3 bit).
For the position of the sample point only the relation (SYNC_SEG + PROP_SEG + PHASE_SEG1) / (PHASE_SEG2) is important. The absolute value of PROPSEG = PROP_SEG is rather of academic interest and is not calculated by the program. The values for PRESDIV, PROPSEG, PSEG1 and PSEG2 are calculated.

Freescale msCAN08, msCAN12 and MCAN

The msCAN module uses two 8-bit registers to set-up the bit timing parameters required by the CAN protocol.

8 bit Bit Timing Register CANBTR1 and CANBTR0 can be calculated selecting NXP SJA1000.

  7 6 5 4 3 2 1 0
CANBTR1 SAMP=0 TSEG2 TSEG1
  7 6 5 4 3 2 1 0
CANBTR0 SJW=0 BRP
For Freescales MCAN use CANBTR1 for register CBT1 (with TSEG2 and TSEG1) and CANBTR0 for CBT0 (with BRP and SJW).

Gridconnect

DSTni ™

Bit rate configuration is done by two 16bit CAN configuration registers Bit Rate Divisor and Configuration.

16 bit Bit Rate Divisor register setting BR

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN
bit rate Div.		 reserved BR[10:0]

16 bit Bit Configuration register setting SJW, SAM, TSEG2 and TSEG1

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN
tsegs		 OVR
MSG		 TS2 TS1 0 AUTO
RES		 SJW SAM EDGE
MODE
TS1=0 and TS1=1 are not allowed; TS2=0 is not allowed; TS2=1 is only allowed in direct sampling mode SAM=0.

gridARM

Bit rate configuration is done by one 32bit CAN configuration register CAN_BR. Prescaler value is 7 bit, 1 to 128.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN_BR reserved SMP - BRP reserved SJW - PROPAG - PHASE1 - PHASE2

This is the same register layout as it can be found in older ATMEL controllers, like the SAM7 or SAMA5 series. To calculate these values, select Atmel AT91SAM9263/SAM7/SAMA5 .

Holt Inc.

Holt Inc. is a provider of analog and mixed signal IC data bus solutions to the avionics industry. The HI-3110 ARINC 825 and CANaerospace Standards compatible controller has an SPI host interface. The bit timing registers are compatible with the NXP SJA1000 CAN. Select this type for calculation of the register values.

IFI - Ingenieurbüro Für Ic-Technologie

IFI is providing FPGA IP cores. The latest one is able to handle enhanced CAN FD protocol. Two 32bit registers are used for setting the arbitration and data bit rate. Both with the same structure.

With the migration from CAN FD non-ISO to the latest ISO standard, IFI changed the Bit-Timing generation and the related register compilation. The non-ISO registers, now know as Timing slow and fast used 4_12_6_6_bit

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SJW prescale time A time B

The CAN FD ISO Bit Timing uses the same registers, now known as Timing slow and fast used: 7_9_8_8_bit

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SJW prescale time A time B

Where time A is the segment before the sample point and time B after.

An additional register at address 0x001c is used to set the transmitter delay.

Infineon

Older 8 and 16 bit and stand alone SAK82C900

The bit timing register model used in the older (Siemens) controllers like C167CR, C515C, XC161C, XC164C, TwinCAN SAK82C900 is very close to the SJA1000, Please use the values calculated for it.

MultiCAN and MultiCAN+

The latest CAN controller family implemented in Infineon controllers is called MultiCAN (or here). The ARM Cortex-M4 XMC4000, Tricore TC1130, AUDO or XC800 families are examples using this CAN core.

On the XMC4500 the 32bit Node Bit Timing Register NBTRx contains all parameters to set up the bit timing for the CAN transfer

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTR reserved 0 DIV8 TSEG2 TSEG1 SJW BRP

MultiCAN+ with extended view to CAN FD

In newer MultiCAN implementations supporting CAN FD the number of possible tq per bit was increased when CAN FD is used. This results in larger values for TSEG[12]. The NBTR register with extended view (NBTEVR) when used with NCR.FDEN = 1.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBT  
EVR		 reserved 0 TSEG1 0 TSEG2 DIV8 0 SJW 0 BRP

The Bit DIV8 when set is used to divide the Prescaler Clock by 8.

The content for the The Fast Node Bit Timing Register, FNBTRx, can be calculated using the "MultiCAN FD FNBTR" selection.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNBTR reserved 0 FTSEG2 FTSEG1 FSJW FBRP

Intel

The old Intel 82527 is not any more manufactured by Intel. But some chips exist to substitute it. The bit timing register is following the NXP SJA1000 model.
Intel has a new chip, Intel® Platform Controller Hub EG20T. It has Bosch D_CAN as CAN module.

IPMS / CAST

IPMS develops and CAST Inc. distributes an CAN IP core called CAN CTRL which is already able to use the CAN FD mode.

Five bit timing registers are used to configure the bit rate for the arbitration phase (S-slow phase) and data phase (F-fast phase).

  7 6 5 4 3 2 1 0
BITTIME_0 F_SJW S_Seg_1
BITTIME_1 F_Seg2 S_Seg_2
BITTIME_2 F_Seg_1 S_SJW
S_PRESC S_PRESC
F_PRESC F_PRESC

This core divides the bit timing into only two parts: The first part called Segment 1 includes the synchronization segment, propagation segment and phase_seg1 and the second part called Segment 2 is equal to phase_seg2.

Currently only the Slow (Classical CAN) bit rate is supported by the calculator.

Kvaser

Kvaser developed there own CAN IP core which is capable of maintaining classic CAN as well as CAN FD.

Unfortunately Kvaser did not provide a detailed CAN register or other interface definition for the CAN IP core. One interface board with up to 4 CAN channels manufactured by Kvaser itself is the PCIEFD.

Nominal and Data Phase Bit Timing (KCAN_BTRN/BTRD)

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTRN - TSEG2 TSEG1 SJW BRP

  • TSEG2 Time Segment 2 setting. Valid range 0..31, TSEG2 = tseg2-1
  • TSEG1 Time Segment 2 setting. Valid range 0..511, TSEG1 = tseg1-1
  • SJW Sync Jump Width setting. Valid range for BTRN and BTRD is 0..15, SJW=tsjw – 1
  • BRP Bit Rate Prescaler setting. Valid range 0..8191 for BTRN. Valid range 0..8191 for BTRD when transmitter delay compensation is disabled and range 0..1 when TRDCE is enabled. BRP=nbrp-1

Microchip

Microchip PIC18F

Microchip use in the PIC18F CPU three 8bit registers. BRGCON1 contains the Prescaler, BRGCON2 the Propagation and Phase Segment 1 bits and BRGCON3 the Phase Segment 2 bits. The last one is only active, if SEG2PHTS (BRGCON2, bit7) is set.

This device, as other of the smaller PIC devices, is not very suitable to implement CANopen. Therefore, bit timing calculation is not yet implemented for it. If someone is interested in using the Timing calculator for simple CAN applications, feel free to implement it here (or pay me to do it).

Microchip dsPIC33F

Enhanced Controller Area Network (ECAN™) The total number of time quanta in a nominal bit time must be programmed between 8 tq and 25 tq. Note 1: (Propagation Segment + Phase Segment 1) must be greater than or equal to the length of Phase Segment 2. Values should be used wth SJW = 1
Example 21-8: CAN Bit Timing Calculation Example (p.58). Step 1: Calculate the time quantum frequency (FCY = 40 MHz). If FBAUD = 1 Mbps, and number of time quanta N = 20, then FTQ = 20 MHz. max prb 64.

CiCFG1 ECAN™ Baud Rate Configuration Register 1

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CiCFG1 unimplemented 0 SJW BRP
Values should be used wth SJW = 0, wich is 1 tq.

CiCFG2 ECAN™ Baud Rate Configuration Register 2

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CiCFG2 - WAK
FIL		 - SEG2PH SEG2
PHTS		 SAM SEG1PH PRSEG
PRSEG - propagation segment
WAK - is not considered in the calculation, add the bit if needed.
WAKFIL: Select CAN Bus Line Filter for Wake-up bit
1 = Uses CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up

Microchip PIC32

The information is valid for the PIC32MX5/6/7 as well as for the latest PI32MZ, Embedded Connectivity (EC) family. The PIC32 family's bit rate prescaler is only programmable between 1 to 64. According to the manual the time quanta is derived by dividing the clock frequency by the factor of two after the bit rate prescaler.
CAN Baud Rate Configuration Register CiCFG is a 32 bit register. It looks like the combination of the two registers used in the dsPIC33.
SEG2PHTS Phase Segment 2 Time Select bit is set to 1, which means Phase Buffer Segment SEG2PH is freely programmable. SAM = SJW = WAKFIL = 0.

FSYS is what you have to enter in the Clock Rate field.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CiCFG 0 WAK
FIL		 0 SEG2PH SEG2
PHTS		 SAM SEG1PH PRSEG SJW BRP

Microchip MCP2510

For anybody using MicroChip's MCP2510, Intrepics has a free Tool to get the timing bits. It is unfortunately a Windows™ only program.
The stand alone controller has three registers to configure the bit timing of the CAN controller.
  • CNF1 controls the bit rate prescaler and the sync jump with.
  • CNF2 the propagation segment, phase segmant 1, SAM bit which controls the number of samples taken at the sample point.
  • CNF3 with phase segment 2, Start-of-Frame signal bit and Wake-up Filter bit.
  7 6 5 4 3 2 1 0
CNF1 SJW BRP
CNF2 BTL SAM PHSEG1 PRSEG
CNF3 SOF WAKFIL - PHSEG2

TODO: calculation is done using BTLMODE = 1. The length of phase segment 2 is determined by the PHSEG2 bits of CNF3.

Microsemi

SmartFusion2

The CAN configuration register CAN_CONFIG is a 32-bit register that is used to configure the functionality of the CAN controller.
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN_CONFIG - CFG_BITRATE - ECR
MODE		 SWAP
ENDIAN		 CFG
ARBITER		 CFG_TSEG1 CFG_TSEG2 AUTO
RESTART		 SJW SAMPLING
MODE		 EDGE
MODE

NXP

NXP is one of the manufacturers still producing a stand alone CAN controller, the famous SJA1000. But also many microcontrollers with integrated CAN and with the LPC11C22 and LPC11C24 parts that include an on-chip, high-speed CAN transceiver.

NXP SJA1000 (NXP, Intel 82527, Infineon TwinCAN .....

The SJA1000 uses only two 8-bit registers to set-up the bit timing parameters required by the CAN protocol. One register BTR0 containing the value of the bit timing prescaler and the other for the values of PHASE_SEG1 and PHASE_SEG2. PHASE_SEG1 is used for programming both (PROP_SEG + PHASE_SEG1) according CAN specification.

  7 6 5 4 3 2 1 0
BTR0 SJW=0 BRP
  7 6 5 4 3 2 1 0
BTR1 SAMP=0 TSEG2 TSEG1

For 125 kbit/s and 16 tq at 16 (8)Mhz - sja100
BTR0 = 3, BTR1 = 1C.
For 125 kbit/s and 16 tq at 20 (10)Mhz - C515C
BTR0 = 4, BTR1 = 1C

LPC11Cx2/Cx4

The LPC11Cx2/Cx4 are ARM Cortex-M0 based, integrating a BOSCH C_CAN module.

nuvoton

nuvoton manufactures the ARM Cortex™-M0 based NuMicro™ family. The two automotive members NUC130/NUC140 have one BOSCH C_CAN module implemented. Select BOSCH C_CAN to generate the bit timing values.

Profichip

Profichip manufactures the SMC1000 ARM9 based SoC with two CAN controllers and dual Ethernet MAC.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BitTime SAM TSEG2 TSEG1 BRP SJW reserved reserved

Renesas

Renesas RX62N/RX621

The RX62N/RX621 Group implements one channel of the CAN module. Bit timing is done writing to the CAN0 Bit Configuration Register (CxBCR). CxBCR consists of 24 bits. A 32-bit read/write access should be performed carefully not to rewrite bits b7 to b0.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CxBCR TSEG1 BRP SJW TSEG2 reserved

Renesas (NEC) V850 µPD70F34x

This family of 32 bit controllers is an originally NEC based product.

Besides the bit rate prescaler, the 8 bit CnGMCS - CANn global clock selection register is used to select the CAN module system clock. It provides the CAN module clock by dividing the CAN clock by 1 to 16 (default).

The 8 bit CnBRP - CANn module bit rate prescaler register holds the 8 bit bit rate prescaler.

The 16 bit CnBTR - CANn module bit rate register is used to program the phase segments phase1 and phase2.

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CnBTR - SJW - TSEG2 - TSEG1

Renesas (Mitsubishi) M32C/87

16bit CANi Configuration Register (CiCONR Register) (i = 0, 1) contains SAM, 3 bit Propagation time segment PTS, 3 bit Phase buffer segment 1 PBS1, 3 bit Phase buffer segment 2 PBS2, SJW.
8bit CANi Baud Rate Prescaler (CiBRP Register) (i = 0, 1) divides by 1 to 256.
Register value restrictions: PTS 1-8, PBS1 2-8, PBS2 2-8.

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CiCONR SJW PBS2 PBS1 PTS SAM -

Renesas RZ family

This new (2013) ARM Cortex A9 based family implements the RS-CAN called module with 32 bit wide registers. RSCAN0CmCFG - Channel Configuration Register (m = 0 or 1) The register can be read/written in 8-, 16-, and 32-bit units, initial value is 0.

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSCAN0CmCFG reserved SJW - TSEG2 TSEG1 reserved BRP

Renesas R-IN family

This new (2013) ARM Cortex M3 based family is promoted as the Renesas Industrial Networking engine.
FCNn is the CAN module name, FCN0 and FCN1. The input of the modules fCAN clock can be selected by the global clock selection register FCNnGMCSPRE to be divided by 1 to 16 before it goes to the module bit rate prescaler register FCNnCMBRPRS (1 to 256). This results in a prescaler divider up to 4096. FCNnCMBRPRS is an 8 bit register.

  7 6 5 4 3 2 1 0
FCNnCMBRPRS FCNnCMBRPRS[7:0]


Bit Timing is set via the 16 bit module bit rate register FCNnCMBTCTL.

  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FCNnCMBTCTL 0 CMBTJWLG 0 CMBTS2LG 0 CMBTS1LG

The manual has a unusual naming: FCNnCMBTJWLG for SJW, FCNnCMBTS1LG for prop seg + TSEG1 and FCNnCMBTS2LG for TSEG2.

Spansion (formerly Fujitsu)

FCR4

Cortex-R4 based family with 3 CAN interfaces implemeting the 16 bit BOSCH C_CAN module. Select "Bosch C_CAN / D_CAN" to calculate the bit timing register values BTR.

ST Microelectronics

bxCAN

The bXCAN module is used in the very popular Cortex M3 family STM32. All relevant parameters are concentrated in one CAN bit timing register (CAN_BTR).

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN_BTR additional bits SJW - TS2 TS1 reserved BRP

The bit timing pre-scaler is 10 bit wide and can divide by 1 to 1024.
Use the table calculated value of BTR and add all additional bits according your requirements to get the final value for CAN_BTR.

SPEAr 300

The SPEAR 300 family implemnts the bit timing registers the same way as the 16 bit BOSCH C_CAN module. 16 bit Bit Timing Register (offset 0x0C) and 16 bit BRP extension register (offset 0x18). Select BOSCH C_CAN for register calculation.

Texas Instruments

TMS320

 The two Texas Instruments families 24xx and 28xx handle the bit timing register slightly different. 240xA is using two 16-bit registers. BCR2 contains the bit pre-scaler in the lowest 8 bits. BCR1 contains valuse of TSEG1 (4-bit) and TSEG2 (3-bit) in the lowest bits 0-6. 281x and 280x are using one 32-bit register BTC for all timing configuration. The BTC value can be combined from BCR1 und BCR2 : (BCR2 << 16) | BCR1

Note that the CPU clock is fed directly to the CAN module (max 150 Mhz for 281x).

There is currently an issue for the high speed controllers in generating low CAN bit rates. For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.

The following is copied fom the manual chapter " 1.1.3 eCAN Compatibility With Other TI CAN Modules"

The eCAN module is identical to the "High-end CAN Controller (HECC)" used in the TMS470TM series microcontrollers from Texas Instruments with some minor changes. The eCAN module features several enhancements (such as increased number of mailboxes with individual acceptance masks, time stamping, etc.) over the CAN module featured in 240xTM series of DSPs. For this reason, code written for 240x CAN modules cannot be directly ported to eCAN. However, eCAN follows the same register bit-layout structure and bit functionality as that of 240x CAN (for registers that exist in both devices) i.e., many registers and bits perform exactly identical functions across these two platforms. This makes code migration a relatively easy task, more so with code written in C language.

The 32 bit Bit-Timing Configuration Register CANBTC
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CANBTC reserved BRP reserved SJW SAM TSEG1 TSEG2

AM335x Sitara

 The latest generation is using the Bosch D_CAN module.

TMS570LS31x/21x

 The TMS570LS31x/21x integrates the ARM® Cortex™-R4F Floating Point CPU designed for Safety Applications. Up to three CAN modules are on chip. The latest generation is using the Bosch D_CAN module.

Stellaris LM3S

 TI's first Cortex-M3 based controllers were developed by the company Stellaris, and baught by TI. These Cortex-M3 controllers implemented the Bosch C_CAN.

Tiva™ C

 The Tiva is the TI Cortex-M4 based controller family (former Stellaris LM4). The Tiva series still implements the Bosch C_CAN module.

CAN Bit Timing register CANBIT

  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CANBIT reserved TSeg2 TSeg1 SJW BRP

For the lower 16 bit the value of BTR calculated when BOSCH C_CAN is selected, can be used.

Toshiba

For the Toshiba TCAN module the calculation results for the NXP SJA1000 can be used.

Xilinx

Xilinx XCAN - Zynq

Xilinx Xcan e.g. integrated into the Xilinx Zynq platform. The Xcan BRPR register and the Xcan BTR register are calculated. Typical clock input frequency is 20Mhz. This can be configured with the Zynq clock module.